The present invention relates to integrated circuit structures, and particularly to on-chip capacitors.
In integrated circuit fabrication, many devices are placed on a single substrate. The various devices must be electrically isolated from one another, but some specific devices must be electrically interconnected to implement a desired circuit function. Many circuits require more than one level of interconnect, so multi-level interconnect structures are used.
One aim of integrated circuit technology is an increase in device speed. This objective has caused integrated circuit fabrication to seek ways of scaling down devices, increasing the functional complexity of the integrated circuit as a whole. However, downscaling of ICs, and therefore speed, is limited by interconnect technology. One problem with multi-level interconnect structures is the filling of high aspect ratio and varying depth contact holes and vias. Many processes have been developed to address these issues. Another problem is the tendency of closely situated conductors to crosstalk, where potential change in one line affects performance of a nearby line.
The damascene process is one method of forming metallized patterns on ICs. First a conductor pattern is etched into a dielectric layer to form grooves within the dielectric layer. A metal is then deposited to fill the etched grooves. Often an interim step is included wherein a diffusion barrier material is deposited on the walls and bottom of the groove to prevent diffusion of the deposited metal into the surrounding dielectric areas. The deposited metal typically covers not only the grooves but the entire surface of the wafer, depending on the method of deposition. This excess metal is removed using a chemical mechanical polish (CMP). This leaves a smooth surface with inlaid metal fingers within the grooves of the dielectric material.
The dual damascene process consists of forming vias and interconnect patterns in the dielectric layer at the same time the original groove is etched. This is followed by a single metal fill that deposits metal in both the grooves and the vias, followed by a polish. The vias in a dual damascene process are often as wide as the metal layer grooves themselves.
Multi-level interconnect structures are also used to form on-chip capacitors. These typically consist of stacked metallized lines connected to two buses which provide the two terminals of the capacitor. Different bus connections are used to give different lines a different polarity. Typically, lines of different polarity are interdigitated, forming a pattern of lines having first one potential, then another.
FIG. 2a shows a conventional on-chip capacitor formed using the existing metal interconnect structure. Note that lines of one polarity are both vertically and laterally adjacent lines of opposite polarity; thus in cross section the conventional has a checkerboard layout.
For many applications, on-chip capacitors are formed from these existing structures of metal lines of alternating polarity. In typical prior art on-chip capacitor structures, multiple levels of interdigitated different polarity metal lines are stacked atop one another (using the above discussed fabrication techniques) to form stacks of metal interconnects. Typically, the metal lines above and below one another are of alternating polarity. Since these metal lines are separated by a dielectric material, they can be used to form on-chip capacitors.
Specifically, CMOS processes for analog applications construct capacitors using these metal interconnects. These structures typically use both the sidewall capacitance (i.e., the capacitance between lines within a single layer) and the xe2x80x9ctop-bottomxe2x80x9d capacitance (i.e., capacitance between two metal lines in adjacent levels of the interconnect structure).
The present application teaches an improvement to on-chip capacitor formation, as discussed below.
The present application discloses a new on-chip capacitor. The vertical stacks of metal lines are oriented so that vertically adjacent lines have the same potential polarity, rather than different polarity. The lines above and below one another are extensively connected by vias, which increases the intralevel or xe2x80x9csidewallxe2x80x9d capacitance of the whole structure (metallization plus via). This necessarily eliminates the top-bottom capacitance contribution provided by vertically adjacent lines of opposite polarity. Though stacking the interconnects in a non-alternating vertical polarity and connecting the vertical stacks by vias sacrifices the interlevel capacitance, the increase in intralevel capacitance more than outweighs this loss. Because the via side wall capacitance can take advantage of a higher dielectric material in its sidewall capacitance, this increases the on-chip capacitance even more.
In one class of embodiments, the vias in the present innovative on-chip capacitor can be extended the entire length of the metal interconnect lines to form walls of metal, increasing intralevel capacitance even further. Likewise, the dielectric constants between the levels (interlevel dielectrics, or ILDs) can be made of a higher dielectric constant material than the gap fill dielectric, or intrametal dielectric fills. This will increase the capacitance between metal lines, increasing on-chip capacitance even more.
The present innovations are particularly useful in that, in some embodiments, they can use the advantages of the dual damascene process or creating metal interconnects, since the metal lines above and below one another are of like polarity. In the dual damascene process, the vias can be made as wide (or wider) than the metal lines themselves, which also increases total capacitance. A further advantage is that in the dual damascene process the dielectric which laterally separates vias does not have to be the same as that which separates metal lines.
Finally, vias can extend above the top-most metal interconnect line and below the bottom-most interconnect line to form xe2x80x9cblindxe2x80x9d vias, increasing the total area of metal and increasing the total capacitance.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following:
greater on-chip capacitance;
minimal alteration of process;
smaller size for the same capacitance;
connections on only one level since the other levels are connected by vias.